Practical, no-fluff writing on ASIC and SoC design — for engineers and for teams evaluating a design partner.
A plain-language walkthrough of what an ASIC is, how it differs from an FPGA, and why companies choose one over the other.
A stage-by-stage look at how a chip goes from RTL code to GDSII — RTL design, verification, DFT, physical design, STA and signoff.
Questions worth asking before you hand off an ASIC or SoC program to an external design team.
