"RTL to GDSII" describes the full journey a chip design takes from a written description of its behavior to a manufacturing-ready layout file. Each stage has its own tools, its own signoff criteria, and its own way of catching different classes of problems before silicon comes back from the fab.
Engineers describe the chip's logic in a hardware description language (Verilog or VHDL) at the register-transfer level — specifying how data moves between registers on every clock cycle. This stage also includes microarchitecture decisions, low-power RTL techniques, and early checks like linting, clock-domain crossing (CDC) and reset-domain crossing (RDC) analysis.
Before any layout work begins, the RTL has to be proven correct. Verification teams build UVM-based testbenches, write assertions, and drive functional coverage up until the design's behavior is exhaustively exercised against the specification. On most programs, verification consumes more engineering time than RTL design itself — bugs caught here are orders of magnitude cheaper to fix than bugs caught in silicon.
Once the logic is verified, DFT engineers insert scan chains, ATPG-ready test structures, and memory built-in self-test (MBIST) so that manufactured chips can actually be tested on a tester after fabrication. Without DFT, there's no practical way to tell a working die from a defective one at volume.
This is where the netlist becomes an actual layout: floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and ECO passes to close on timing and power. Physical design is where the process node's design rules stop being abstract and start dictating real constraints on every decision.
STA checks that every signal path in the design meets timing across every operating corner — voltage, temperature and process variation combined. Constraint development and multi-corner, multi-mode (MMMC) analysis run continuously alongside physical design, not just at the end.
Before tapeout, the design goes through DRC (design rule checking), LVS (layout-versus-schematic), antenna and density checks, and final signoff review. Once every check is clean, the design is released as GDSII — the file format the foundry actually manufactures from.
Every stage above is its own specialty in practice, which is exactly why most ASIC programs are staffed by teams rather than individuals — and why the handoffs between stages are usually where schedules slip if they aren't planned for upfront.
